As is well known in the art, digital and linear functions are often performed by integrated circuits using either bipolar or metal-oxide-semiconductor (MOS) technology. Bipolar integrated circuits, of course, provide higher speed operation and greater drive currents than the MOS circuits, at the cost of higher power dissipation, especially when compared against complementary MOS (CMOS) circuits. Recent advances in manufacturing technology have allowed the use of both bipolar and CMOS transistors in the same integrated circuit (commonly referred to as BiCMOS devices). An example of a BiCMOS structure is described in copending application Ser. No. 481,804 filed Feb. 20, 1990 (filed as a continuation of Ser. No. 008,910, filed Jan. 30, 1987) and assigned to Texas Instruments Incorporated.
The formation of BiCMOS devices may of course be accomplished by forming the bipolar transistors according to known techniques in selected areas of the device, by additionally forming the MOS transistors according to known techniques in selected areas of the device, and interconnecting the two types of transistors. However, certain features of each type of transistor tend to be incompatible, from a process standpoint, with the other type, requiring a large number of process steps to form each. It is therefore preferable in the manufacture of such BiCMOS circuits to utilize structures which are useful in both types of transistors, in order to minimize the process complexity and cost. Such dual utilization of structural components and process steps, however, generally results in a process which is less than optimal for either the bipolar or the MOS transistors, or both.
Prior methods for forming the bipolar transistors in such structures have incorporated thin oxide layers between the diffused base region and the overlying emitter electrode (generally formed of polysilicon). The thin oxide over the base is generally formed in the same step as the gate oxide for the MOS transistors, and therefore is generally of a thickness on the order of 20 nm.
Such thin oxides separating the base region from the emitter electrode cause certain problems, however. First, performance of the bipolar transistors degrades as the emitter-to-base capacitance increases. Of course, such capacitance increases as the dielectric thickness therebetween decreases, making it preferable to have a thicker dielectric between the emitter and the base region. Second, a thin dielectric between the emitter electrode and the base region is inherently more susceptible to stress from subsequent processing steps such as contact etch, silicidation, and metal deposition and sinter. Third, a thin dielectric also increases the risk that a contact via formed over the oxide for connecting an overlying metallization layer to the emitter electrode will leak to the base region. This can occur in the event that the contact via is overetched through the emitter electrode, in which case the dielectric under the emitter electrode will be further thinned, in turn further increasing the emitter-to-base capacitance. In extreme cases, the dielectric may be etched completely through, shorting the overlying metal and the emitter electrode to the base region.
The method described in the above-referenced application, Ser. No. 008,910, using the thin MOS gate oxide and thin dielectric over the base region, avoids the stress and overetch problems by making contact to the polysilicon emitter electrode at a location away from the contact to the base region. Such a configuration does not, however, address the emitter-to-base capacitance problem, and adds the disadvantage of increasing the emitter resistance.
But, the use of a relatively thick base oxide creates its own problems. For example, the thinner gate oxide areas provide a constraint on the extent to which the base oxide may be etched. Thus in copending application Ser. No. 07/366,244 filed Jun. 12, 1989 (as a continuation of Ser. No. 07/129,271 filed Dec. 7, 1987), a gate oxide is removed from source and drain regions prior to the reach-through implant. Removal of the extrinsic region of the thicker oxide requires either masking of source/drain regions or deleterious overetching thereof. Thus an extra processing step is required because of the thickness of the base oxide.
It will also be appreciated that the sidewall filament in the vicinity of base oxide will likewise be adversely affected by the degree of overetching required to remove the extrinsic portion of the base oxide.
It is therefore an object of this invention to provide a process for forming a BiCMOS structure which incorporates a substantially thicker dielectric layer between the base and emitter of the bipolar transistors.
Another object of this invention is, specifically, to provide such a process having such a thicker dielectric in a manner compatible with the formation of the MOS transistors in the same structure, and without requiring an additional masking step at the source/drain regions of the MOS transistors to etch the base oxide.
It is yet another object of this invention to provide such a process which provides a relatively thick base oxide without requiring either deleterious over-etching of the source/drain regions or the sidewall oxides.
Other objects and advantages of the invention will be apparent to those of ordinary skill in the art having reference to the following specification in conjunction with the drawings.